In a serializer/deserializer (SerDes) circuit, in order to correctly transmit a signal to be converted, transmitters (TX) constituting lanes needs to be synchronized accurately. For example, when parallel signals are converted into serial signals, parallel signals inputted to the transmitters constituting lanes need to be synchronized appropriately. One method to distribute signals appropriately to the transmitters is to synchronize by using a high-speed clock signal having the same frequency as the frequency of the serial signals. When a synchronization signal is asserted for the transmitters, the high-speed clock signal with the same frequency as the frequency of the serial signals is transmitted to the transmitters.
At this time, paths for the high-speed clock signal become effective all at once, and hence a load current flowing through the circuits increases rapidly. Then the voltage of a low drop out (LDO) voltage regulator drops largely, deteriorating quality of the high-speed clock signal. By this deterioration in quality of the high-speed clock signal, a divider of each transmitter may consequently become unable to divide the clock signal correctly, which may result in a failure of the synchronization. Further, not only does the voltage of the regulator on the side transmitting the clock signal drops, but also the voltage on the transmitter side drops because the load current increases similarly in the regulator on each transmitter side.
In order to prevent this drop in voltage, it is conceivable to place a stabilization circuit to stabilize the voltage. However, placing the stabilization circuit raises a concern that the area of the entire SerDes circuit increases by the area occupied by the stabilization circuit.